1. Technical Field of the Invention
The present invention relates to a clock converter using a phase locked loop (PLL) circuit and an electronic apparatus using the same, and more particularly, to a clock converter for multiplying a basic clock signal from several kilohertz (for example, 8 kHz) to several hundred megahertz (for example, 622.08 MHz) with a clock signal of a high frequency no less than several hundred megahertz (for example, 622.08 MHz), and to an electronic apparatus using the same.
2. Related Art
Communication apparatuses such as telephones, mobile telephones, facsimiles, and personal computers (PC) transmit and receive communication data with the speed of a clock signal increased by a clock converter. Also, the bandwidth of communication networks has recently been increased. Accordingly, data need to be transmitted and received in a high frequency band that is more than 400 MHz, according to market requirements. A clock converter for coping with an increase in communication speed requires high frequency stability for high frequency bands, temperature compensation for an oscillation frequency within the operating temperature range of the communication apparatus, and a small amount of jitter of a clock signal output from an oscillation circuit.
Furthermore, in order to convert a clock signal to have high speed, it is necessary that an input clock signal be synchronized with an output clock signal in a clock converter. Accordingly, a multiplication ratio of the input and output clock signals is a integer. It is necessary that the rising and falling waveforms of the input clock signal and the output clock signal coincide with each other. In order to realize such characteristic conditions, in general, phases are synchronized and a frequency is multiplied by the clock converter using a PLL circuit. Recently, a clock converter for high speed communications for multiplying a basic clock signal of several kilohertz (for example, 8 kHz) to a high frequency clock signal no less than several hundred megahertz (for example, 622.08 MHz) is also realized as the communication speed increases.
An oscillation frequency of the clock converter is determined by a VCO (voltage controlled oscillator). Also, because, for example, an AT crystal oscillator oscillating by several tens MHz is used as an oscillation device of the VCO, such a VCO is referred to as a VCXO (voltage controlled X'tal oscillator).
FIG. 9 is a conceptual view illustrating the structure of a general VCXO. In FIG. 9, an oscillator 18 generates a signal of a predetermined frequency on the basis of the oscillation of an AT crystal oscillator 17. At this time, in order to output a signal of a high frequency no less than several hundred megahertz, a frequency multiplier 19 is provided to multiply an oscillation frequency from the oscillator 18 by an integer and to output a signal of a predetermined high frequency. Recently, there exists an AT oscillator of more than 100 MHz. In this case, it is possible to output a signal of a high frequency of no less than several hundred megahertz without the frequency multiplier 19. Also, it is possible to differentially output a plurality of output signals from a differential converter 20 in consideration of an interface with a load circuit.
FIG. 10 is a block diagram illustrating a structure of a conventional clock converter. A clock converter 1′ includes a phase detector IC chip 2 (phase detector means), a LPF (low pass filter) 3, a VCXO (voltage controlled X'tal oscillator) 4′ and a signal transmitting circuit 5. The phase detector IC chip 2 includes a phase detector circuit (PD) 6, a feedback frequency dividing circuit (1/N) 7 and an input frequency dividing circuit (1/P) 8. The structure of the clock converter 1′ is the same as the structure of a common PLL circuit. The detailed description of the operations of the respective members is omitted. For example, clock signals CK+ and CK− of, for example, 20 MHz input to the clock converter 1′ are multiplied to clock signals OUT+ and OUT− of, for example, 100 MHz and are output.
In order to PLL feedback an output signal of the VCXO 4′, a PLL feedback loop is formed from a differential amplifying circuit, which is formed of an ECL, of a output step (not shown) in the VCXO 4′ to an input step of the feedback frequency dividing circuit 7 of the phase detector IC chip 2 through the signal transmitting circuit 5. Also, because a PECL (positive emitter coupled logic) is commonly used as the differential amplifying circuit of the output step of the VCXO 4′, hereinafter, the differential amplifying circuit may be referred to as a PECL. The input step of the feedback frequency dividing circuit 7 in the phase detector IC chip 2 may be formed of the differential amplifying circuit (that is, the PECL) or a differential CMOS circuit.
FIG. 11 is a block diagram of a signal transmitting circuit positioned between the PECL of the output step of the VCXO and the PECL of the input step of the feedback frequency dividing circuit 7 of the phase detector IC chip in the clock converter illustrated in FIG. 10. That is, FIG. 11 illustrates the interface between the PECL of the output step of the VCXO (hereinafter, a VCXO·PECL 4′a) and the PECL of the input step of the feedback frequency dividing circuit 7 of the phase detector IC chip 2 (hereinafter, a feedback frequency dividing circuit·PECL 7a). At this time, the impedance standard of the interface between the VCXO·PECL 4′a and the feedback frequency dividing circuit·PECL 7a is 50 Ω. Therefore, two transmission line of impedances Z1 and Z2 (wherein each transmission line has impedance of 50 Ω) connect between output terminals T′2 and T′3 of the VCXO·PECL 4′a and input terminals T7 and T8 of the feedback frequency dividing circuit·PECL 7a. Furthermore, the voltage applied to each termination of the feedback frequency dividing circuit·PECL 7a having the transmission line impedances Z1 and Z2 is divided by a bias resistance.
FIG. 12 is a block diagram of a signal transmitting circuit between the PECL of the output step of the VCXO and the differential CMOS of the input step of the feedback frequency dividing circuit 7 in the clock converter illustrated in FIG. 10. That is, FIG. 12 illustrates the interface between the PECL of the output step of the VCXO (the VCXO·PECL 4′a) and the differential CMOS of the input step of the feedback frequency dividing circuit 7 (the feedback frequency dividing circuit differential CMOS 7b). One wiring line has an AC coupling capacitor C51 midway, and the other wiring line is terminated by a resistor R56 at the VCXO·PECL 4′a and is terminated by a parallel circuit of a capacitor C52 and a resistor R54 at the feedback frequency dividing circuit differential CMOS 7b side, between the output terminals T′2 and T′3 of the VCXO·PECL 4′a and the input terminals T7 and T8 of the feedback frequency dividing circuit·differential CMOS 7b. 
That is, in the conventional clock converter 1′, as illustrated in FIG. 10, the two wiring lines of the PLL feedback loop are drawn out from the output terminals T2 and T3 of the VCXO 4′ and connected to the input terminals T7 and T8 of the feedback frequency dividing circuit 7 in the phase detector IC chip 2 through the signal transmitting circuit 5. In particular, when a feedback signal of a clock signal no less than several hundred megahertz is transmitted by the PLL feedback loop, it is necessary that the impedance matching be taken in the interface between an input and an output, or transmission lines. Therefore, the impedance is matched by establishing transmission line impedances Z1 and Z2 of 50 Ω as the interface between an input and an output as illustrated in FIG. 11 or by connecting a resistor or a capacitor to input and output as illustrated in FIGS. 11 and 12.
When a load circuit is connected to the output of the clock converter 1′, it has a negative influence that the output signals OUT+ and OUT− of the VCXO 4′ change or the waveform amplitudes of the output signals OUT+ and OUT− reduce due to the operation state of load. Therefore, a PLL feedback signal by a PLL feedback loop becomes unstable. Accordingly, hunting may be caused in the overall system of the clock converter 1′. In order to reduce the bad influences of the PLL feedback loop, measures for reducing the influences of the load circuit of the PLL feedback loop by connecting a buffer circuit (not shown) to the output of the VCXO 4′ are taken. However, in order to provide such means, it is necessary to determine component constants by cut and try caused by actual load and to add a large number of parts. Accordingly, it is impossible to minimize the clock converter 1′ and to reduce the price of the clock converter 1′.
Furthermore, in the case of using the AT crystal oscillator 17 as the oscillation device as illustrated in FIG. 9, the principal vibration and secondary vibration are simultaneously excited. Accordingly, many resonance points exist. Moreover, the frequency multiplier 19 generates a high frequency of integer times as large as the principal vibration. Accordingly, spurious or noise exists in an output signal to thus generate jitter in the output signal. Therefore, it is impossible to reduce jitter. Furthermore, the VCXO may be large-sized by providing the frequency multiplier 19.
Also, as illustrated in FIG. 11, in the case where both the differential amplifying circuit of the VCXO and the differential amplifying circuit of the feedback frequency dividing circuit 7 are PECLs, the PECLs are commonly used for a clock converter where a conversion frequency is no less than several hundred megahertz (for example, 622.08 MHz). However, it causes various problems as follows. Firstly, because a power source and a ground in each functional block in FIG. 10 are shared and have low impedance, when the electric potential of the power source or the ground changes, noise overlaps, thus mutually influencing each functional block. For example, the switching noise in the phase detector circuit 6 is transmitted to another functional block such as the VCXO 4′ through the power source or the grand.
Secondly, the substrate, on which the respective parts of the clock converter 1′ are mounted, is small such that the size of the substrate is about 20 mm×30 mm. Therefore, it is impossible to isolate the parts from each other because the parts are close to each other. Accordingly, the parts are easily electronically coupled or capacitively coupled with each other and electrically have bad influences on each other. Thirdly, although a differential amplifying circuit where a S/N ratio is excellent by removing differential noise caused by a differential operation is used, because the size of the substrate is restricted, it is impossible to form a differential amplifying circuit so as to be operated by a plurality of input and output signals in the respect of space. Fourthly, it is a standard specification to use a strip line of 50 Ω as transmission line impedances Z1 and Z2 in the high frequency circuit in which clock signal has a frequency no less than, for example, 200 MHz when a signal is transmitted and received as illustrated in FIG. 11. However, a wiring space is needed for forming the transmission line impedances Z1 and Z2. As a result, there occurs a problem that the clock converter 1′ is large-sized.
Also, as illustrated in FIG. 12, when the differential amplifying circuit of the VCXO is the PECL and the differential amplifying circuit of the feedback frequency dividing circuit 7 is the CMOS circuit, which is commonly used for a clock converter where a conversion frequency is no more than 100 MHz, it causes the following problem. That is, as illustrated in FIG. 12, when the bias voltage of the VCXO·PECL 4′a is different from the bias voltage of the feedback frequency dividing circuit·differential CMOS 7b, it is necessary to connect the AC coupling capacitor C51 between the input and the output of the PLL feedback loop. Therefore, it is necessary to directly connect a termination resistor R55 to the VCXO·PECL 4′a and drop the termination resistor R55 to the ground.
Furthermore, in this case, it is necessary that the value of the termination resistor R55 be equal to 50 Ω, the impedance value of the transmission line impedances Z1 and Z2 shown in FIG. 11. Therefore, the current flowing through the termination resistor R55 varies according to a power source voltage, however, significantly increases to, for example, 50 to 60 mA. Accordingly, the power consumption increases, which is not suitable for reducing power consumption. When the power source voltage supplied to the clock converter is Vcc, the bias voltage is commonly Vcc-2V in the VCXO·PECL 4′a and ½ Vcc in the feedback frequency dividing circuit·differential CMOS 7b. 
According to the above problems, one object of the present invention is to provide a clock converter, which is miniaturized by reducing a wiring pattern and outputs a stable clock signal of high frequency by performing a PLL feedback so as not to be affected by a load circuit and, and an electronic apparatus with the same.